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include/we-aut_sys/enc28j60.h File Reference

Overview

weAutSys' (weAut_01's) 28J60 Ethernet driver

This file contains the definitions of (low level) system calls and services for the weAutSys' (weAut_01's) 28J60 Ethernet driver.

This is system software and must not be modified for user or application programs.

This file is part of weAutSys   <weinert-automation.de>


  Copyright © 2011 Albrecht Weinert, Bochum

Author:
Albrecht Weinert   <a-weinert.de>
Revision:
2
Date:
2017-01-25 17:49:03 +0100 (Mi, 25 Jan 2017)

Defines

#define BFC_CMD
 Bit field clear command.
#define BFS_CMD
 Bit field set command.
#define COLSTAT
 collision is occurring (Bit number)
#define deSelectEnc()
 De-select the ENC28J60.
#define DPXSTAT
 configured for full-duplex (Bit number)
#define ENCBUF_END   0x1FFF
 ENC's dual port RAM end.
#define FRCLNK
 make link up even when no partner station detected (Bit number)
#define HDLDIS
 half duplex loopback disable (Bit number)
#define JABBER
 turn jabber correction off (Bit number)
#define JBSTAT
 transmission met jabber criteria since last PHSTAT1 read
#define LA_BFAST
 see PHLCON
#define LA_BSLOW
 see PHLCON
#define LA_COL
 see PHLCON
#define LA_DSC
#define LA_DSTAT
 see PHLCON
#define LA_LEDOFF
 see PHLCON
#define LA_LEDON
 see PHLCON
#define LA_LSRX
 see PHLCON
#define LA_LSTAT
 see PHLCON
#define LA_LSTXRX
 see PHLCON
#define LA_RX
 see PHLCON
#define LA_RXTX
 see PHLCON
#define LA_TX
 see PHLCON
#define LB_BFAST
 see PHLCON
#define LB_BSLOW
 see PHLCON
#define LB_COL
 see PHLCON
#define LB_DSC
 see PHLCON
#define LB_DSTAT
 see PHLCON
#define LB_LEDOFF
 see PHLCON
#define LB_LEDON
 see PHLCON
#define LB_LSRX
 see PHLCON
#define LB_LSTAT
 see PHLCON
#define LB_LSTXRX
 see PHLCON
#define LB_RX
 see PHLCON
#define LB_RXTX
 see PHLCON
#define LB_TX
 see PHLCON
#define LLSTAT
 link was up continuously since last PHSTAT1 read
#define LSTAT
 link is currently up (Bit number)
#define NOSTRCH
 do not stretch LED events (see PHLCON)
#define PFDPX
 full duplex capable (bit 12 is always set)
#define PHCON1
 PHY control register 1.
#define PHCON2
 PHY control register 2.
#define PHDPX
 half duplex capable (bit 11 is always set)
#define PHID1
 PHY identification register 1.
#define PHID2
 PHY identification register 2.
#define PHIE
 PHY interrupt enable register.
#define PHIR
 PHY interrupt request register.
#define PHLCON
 LED Configuration Register.
#define PHSTAT1
 PHY status register 1.
#define PHSTAT2
 PHY status register 2.
#define PLRITY
 polarity of TPIN is reversed
#define RBM_CMD
 Read buffer memory command.
#define RCR_CMD
 Read control register command.
#define RXBUF_END   0x1A0D
 Receive buffer end.
#define RXSTAT
 PHY is currently receiving (Bit number)
#define selectEnc()
 Chip select the ENC28J60.
#define SYSRST_CMD   0xFF
 Reset ENC28J60 command.
#define TLSTRCH
 LED pulse stretch, long 140ms (see PHLCON)
#define TMSTRCH
 LED pulse stretch, medium 70ms (see PHLCON)
#define TNSTRCH
 LED pulse stretch, normal 40ms (see PHLCON)
#define tranceiveEnc(sendB)
 Transmit and receive one byte to / from ENC28J60.
#define tranceiveEnc2(sendB1, sendB2)
 Transmit two bytes and receive one byte to / from ENC28J60.
#define TXBUF_STRT   0x1A0E
 Transmit buffer start.
#define TXDIS
 disable twisted-pair transmitter hardware driver (Bit number)
#define TXSTAT
 PHY is currently transmitting (Bit number)
#define WBM_CMD
 Write buffer memory command.
#define WCR_CMD
 Write control register command.
Control registers
#define ESTAT
 ETHERNET status register.
#define CLKRDY
 Clock (oscillator) is ready (ESTAT bit number)
#define TXABRT
 The transmit request was aborted (ESTAT bit number)
#define ECON2
 ETHERNET control register 2.
#define AUTOINC
 automatic increment and wrap of RAM buffer addresses (ECON2 bit number)
#define PKTDEC
 decrement (received) packets count (ECON2 bit number)
#define PWRSV
 switch the PHY interface off (save power when not needed; ECON2 bit number)
#define VRPS
 only if PWRSV set voltage regulator to low current (ECON2 bit number)
#define ECON1
 ETHERNET control register 1.
#define TXRST
 Transmit only reset (ECON1 bit number)
#define RXRST
 Receive only reset (ECON1 bit number)
#define DMAST
 DMA operation (within internal RAM) start and busy bit (ECON1 bit number)
#define CSUMEN
 DMA hardware calculates checksums (ECON1 bit number)
#define TXRTS
 The transmit logic is attempting to transmit a packet (ECON1 bit number)
#define RXEN
 Receive enable.
#define EIE
 Ethernet interrupt enable register.
#define INTIE
 EIE bit number
#define PKTIE
 EIE bit number
#define DMAIE
 EIE bit number
#define LINKIE
 EIE bit number
#define TXIE
 EIE bit number
#define TXERIE
 EIE bit number
#define RXERIE
 EIE bit number
#define EIR
 Ethernet interrupt request register.
#define PKTIF
 EIR bit number
#define DMAIF
 EIR bit number
#define LINKIF
 EIR bit number
#define TXIF
 EIR bit number
#define TXERIF
 EIR bit number
#define RXERIF
 EIR bit number
Per packet control bits for transmission settings
#define PHUGEEN
 Huge frame enable (bit number)
#define PPADEN
 per packet padding enable (bit number)
#define PCRCEN
 per packet CRC enable (bit number)
#define POVERRIDE
 packet overrides (bit number)

Symbolic names for direct register access

The lower 5 bits (0..31) give the register number in each bank.

The bits 5 and 5 (mask 0x60) are used for the bank number (0..3 * 32).

#define ERDPTL
 The buffer read address register.
#define ERDPTH
 the buffer read address register
#define EWRPTL
 The buffer write address register.
#define EWRPTH
 the buffer write address register
#define ETXSTL
 The write / transmit buffer range.
#define ETXSTH
 the write buffer range
#define ETXNDL
 the write buffer range
#define ETXNDH
 the write buffer range
#define ERXSTL
 The read / receive buffer range.
#define ERXSTH
 the write buffer range
#define ERXNDL
 the write buffer range
#define ERXNDH
 the write buffer range
#define ERXRDPTL
 The receive buffer (already) read address register.
#define ERXRDPTH
 receive buffer already read
#define ERXWRPTL
 The receive buffer write address register.
#define ERXWRPTH
 receive buffer write
#define EDMASTL
 DMA start low byte.
#define EDMASTH
 DMA start high byte.
#define EDMANDL
 DMA end low byte.
#define EDMANDH
 DMA end high byte.
#define EDMADSTL
 DMA destination low byte.
#define EDMADSTH
 DMA destination high byte.
#define EDMACSL
 DMA checksum low byte.
#define EDMACSH
 DMA checksum high byte.
#define EHT0
 hash table byte 0
#define EHT1
 hash table byte 1
#define EHT2
 hash table byte 2
#define EHT3
 hash table byte 3
#define EHT4
 hash table byte 4
#define EHT5
 hash table byte 5
#define EHT6
 hash table byte 6
#define EHT7
 hash table byte 7
#define EPMM0
 pattern match mask byte 0
#define EPMM1
 pattern match mask byte 1
#define EPMM2
 pattern match mask byte 2
#define EPMM3
 pattern match mask byte 3
#define EPMM4
 pattern match mask byte 4
#define EPMM5
 pattern match mask byte 5
#define EPMM6
 pattern match mask byte 6
#define EPMM7
 pattern match mask byte 7
#define EPMCSL
 pattern match checksum low byte
#define EPMCSH
 pattern match checksum high byte
#define EPMOL
 pattern match offset low byte
#define EPMOH
 pattern match offset high byte
#define ERXFCON
 Ethernet receive filter control register.
#define EPKTCNT
 Ethernet package count.
#define MACON1
 MAC control register 1.
#define TXPAUS
 MAC control register 1 (bit number)
#define RXPAUS
 MAC control register 1 (bit number)
#define PASSALL
 MAC control register 1 (bit number)
#define MARXEN
 MAC control register 1 (bit number)
#define MACON2
 MAC control register 2 (inofficial)
#define MACON3
 MAC control register 3.
#define PADCFG2
 MAC control register 3 (bit number)
#define PADCFG1
 MAC control register 3 (bit number)
#define PADCFG0
 MAC control register 3 (bit number)
#define EXPSF64
 All short frames will be padded to 64 Bytes and have valid CRC appended.
#define EXPSF60
 All short frames will be padded to 60 Bytes and have valid CRC appended.
#define NOSFPAD
 No handling short frames.
#define DTCTVLAN
 Automatic handling short frames.
#define TXCRCEN
 MAC control register 3 (bit number)
#define PHIDREN
 MAC control register 3 (bit number)
#define HFRMEN
 MAC control register 3 (bit number)
#define FRMLNEN
 MAC control register 3 (bit number)
#define FULDPX
 MAC control register 3 (bit number)
#define MACON4
 MAC control register 4.
#define DEFER
 MAC control register 4 (bit number)
#define BPEN
 MAC control register 4 (bit number)
#define NOBKOFF
 MAC control register 4 (bit number)
#define MABBIPG
 back-to-back inter-packet gap
#define MAIPGL
 non back-to-back inter-packet gap low
#define MAIPGH
 non back-to-back inter-packet gap high
#define MACLCON1
 retransmission maximum (4 bit)
#define MACLCON2
 collision window (6 bit)
#define MAMXFLL
 maximum frame length low byte
#define MAMXFLH
 maximum frame length high byte
#define MICMD
 MII command register.
#define MIISCAN
 MII command register (bit number)
#define MIIRD
 MII command register (bit number)
#define MIREGADR
 MII register address register.
#define MIWRL
 MII write data low byte.
#define MIWRH
 MII write data high byte.
#define MIRDL
 MII read data low byte.
#define MIRDH
 MII read data high byte.
#define MAADR1
 MAC address register (first)
#define MAADR2
 MAC address register.
#define MAADR3
 MAC address register.
#define MAADR4
 MAC address register.
#define MAADR5
 MAC address register.
#define MAADR6
 MAC address register (last)
#define EBSTSD
 built-in self test fill seed
#define EBSTCON
 Ethernet self test control register.
#define EBSTCSL
 built-in self test checksum low byte
#define EBSTCSH
 built-in self test checksum high byte
#define MISTAT
 MII status register.
#define NVALID
 MII status register (bit number)
#define SCAN
 MII status register (bit number)
#define BUSY
 MII status register (bit number)
#define EREVID
 Ethernet revision ID (5 bit, R/O)
#define ECOCON
 Clock output control.
#define EFLOCON
 EFLOCON (Ethernet Flow Control.
#define EPAUSL
 Pause timer value low byte.
#define EPAUSH
 Pause timer value high byte.
#define REG_MASK   0x1F
 Mask for register number bits in symbolic register address.
#define REG_BANK_MASK   0x60
 Mask for bank bits in symbolic register address.
#define SPI_BANK_MASK
 Mask for bank bits in control register.
#define KEY_REGISTERS   0x1B
 First number of common registers.
uint8_t currentBank
 The currently set bank of registers.

Functions

void clearBitfield (uint8_t regAdd, uint8_t data)
 Clear bits in a control register.
void encDisablePowersave (void)
 Leave the power safe mode.
void encEnablePowersave (void)
 Go to power safe mode.
void encGetMacAdd (eth_addr_t *mac)
 Read the current MAC address.
void encInit (void)
 Initialise the Ethernet controller ENC28J60.
void encReset (void)
 Reset the Ethernet controller ENC28J60.
void encSetBufferLimits (void)
 Set the sizes of ENC28J60's receive and transmit buffers.
uint8_t encSetMacAdd (eth_addr_t *mac)
 Set the MAC address.
void putBufferMemory (uint8_t data)
 Write one byte to ENC28J60's memory buffer.
void readBufferMemory (uint8_t *dest, uint16_t n)
 Read n bytes from ENC28J60's memory buffer.
uint8_t readControlRegister (uint8_t regAdd)
 Read a control register.
uint16_t readPhysicalRegister (uint8_t regAdd)
 Read one of ENC28J60's physical registers.
uint8_t setBank (uint8_t regAdd)
 Sets a register bank (in ECON1) if necessary for the given register.
void setBitfield (uint8_t regAdd, uint8_t data)
 Set bits in a control register.
void writeBufferMemory (uint8_t *source, uint16_t n)
 Write n bytes to ENC28J60's memory buffer.
void writeControlRegister (uint8_t regAdd, uint8_t data)
 Write a control register.
void writePhysicalRegister (uint8_t regAdd, uint16_t data)
 Write to one of ENC28J60's physical registers.

Variables

uint16_t actPackInd
 Index of the actual receive packet in ENC's dual port memory.
uint8_t receiveStatVec []
 Receive status vector.
uint8_t transmitStatVec []
 Transmission status vector.